Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
High speed data transmission, such as transmission obtained through fiber-optical networking systems, and high speed data processing required for high speed storage devices requires efficient error correcting codes that can support high throughput to meet continuing demands of higher data rates. Reed-Solomon (RS) codes are popularly used in various storage and communication applications because of their guaranteed burst error correction capability. However, implementing a high speed and area efficient RS decoder architecture has always been a key challenge. Developing a suitable RS decoder architecture always requires a trade-off between throughput, area, and latency.
State of the art hard decision (HD) RS decoders implemented on FGPA hardly reach a maximum throughput of 2 Gbps. A recently released Xilinx's RS decoder IP supports a maximum throughput of 3.2 Gbps for the RS (255,239) code. Altera RS IP core also supports a maximum throughput of 3 Gbps for the RS (204,188) code.
As one may be aware, there are mainly two categories of decoding: algebraic Soft-Decision Decoders (SDD) and Hard-Decision Decoders (HDD), where SDD provides better correction performance than HDD with higher complexity. However, SDD requires large area for implementation. First and popular SDD based on Koetter-Vardy (KV) algorithm includes three main steps: multiplicity (m) assignment, interpolation, and factorization. One major problem of KV like architectures is that the SDD based on KV algorithm requires larger area due to complexity of interpolation and factorization steps.
Another issue with existing RS decoders is that it does not provide flexibility in terms of error correcting capabilities. Most of the existing RS decoders are configured with fixed error correction capability and perform decoding irrespective of channel characteristics and performance.
There is therefore a need in the art for a configurable RS decoder and a method thereof that can choose error correcting capability depending on channel characteristics and performance A RS decoder and a method of implementation/working thereof is also required to achieve high throughput and low latency for high speed storage and high speed transmission systems.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by a reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.